DEVS 형식론에 의한 하드웨어 모델링 및 합성가능한 VHDL Code의 자동 생성 = Hardware modeling based on DEVS formalism and automatic generation of synthesizable VHDL code

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Advisors
박규호researcherPark, Kyu-Horesearcher
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
1996
Identifier
108801/325007 / 000953445
Language
kor
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 1996.8, [ vii, 91 p. ]

Keywords

합성가능한 VHDL; HDEVS 형식론; 하드웨어 모델링; DEVS 형식론; VHDL Code 자동 생성; VHDL code Generation; Synthesizable VHDL; HDEVS formalism; Hardware modeling; DEVS formalism

URI
http://hdl.handle.net/10203/36880
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=108801&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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