In Through-silicon via (TSV) based three-dimensional integrated circuit (3-D IC), three-dimensional interconnections are expected to realize considerable high bandwidth throughput in vertically stacked and laterally distributed ICs. However, although TSVs and a silicon interposer in TSV-based 3-D IC lead to a significant decrease of interconnect length, the received digital signal is still degraded at high data rate due to non-idealities of 3-D IC channel. Therefore, analysis of signal integrity in 3-D IC is necessary.
The eye-diagram, which is a convenient and graphical method to analyze received digital signal, is usually used for analyzing the signal integrity. However, the simulation and measurement of the eye-diagram have several limitations, such as time consuming and fabrications of 3-D IC test vehicles. Moreover, though there has been the previous works for estimating the eye-diagram, these methods have the limitations of accuracy and the estimation time.
In this thesis, the precise and fast eye-diagram estimation method is proposed, verified and applied to the optimization of the 3-D IC channels. As mentioned before, the previous eye-diagram estimation methods have several limitations, because they use the simplified channel model or time-consuming processes. Therefore, the proposed method uses the equivalent-circuit model of 3-D IC channel and the equation-based calculation, and they compensate the accuracy and the estimation time, respectively. For verifying the accuracy and the fast estimation time, the comparison result between the proposed method and the full-wave simulation are presented. The result shows that the estimated eye-diagram using the proposed method is almost same with the eye-diagram using the full-wave simulation, and the estimation time is much faster. Moreover, the verification result of the proposed method by measuring the fabricated test vehicles, which contain TSV and the silicon interposer interconnect, are also presented.