Investigation on the structural dependence of source-drain for capacitorless DRAM

Abstract

Capacitorless DRAM can be considered as a one of promising candidate of next generation DRAM application as scaling down. It is utilized the inherent property of floating body cell, e.g., SOI.. Impact ionization and GIDL methods was introduced to operates the DRAM cell. Recently, the parasitic BJT method was proposed to improve the memory performance including sensing margin, operation speed, and scalability. However, the hold-retention time is yet insufficient for DRAM application. In this point of view, the underlap device was proposed for the enhanced hold-retention time. In this dissertation, the improved hold-retention characteristics are proved on the experimental basis. The underlap structure shows the better hold-retention characteristic due to the reduced Shockely-Read-Hall recombination and Gate-Induced-Drain-Leakage current. Furthermore, it shows the wider operation window of program drain voltage and improved maximum sensing current due to the unique property of that structure. The larger sensing current can provides better operation speed, and scalability. And the better immunity for noise is attained due to the wider operation window of program drain voltage. Therefore, considering all of this, the underlap structure can be a leading candidate of capacitorless DRAM.