As the high performance multi-processing demands in battery-based mobile systems increase, the clock synchronization circuit is required in various mobile applications including memory interface. This clock synchronization circuit should have a fast lock time for fast wake-up from power-down mode that enables to reduce the system’s power consumption.
A clock-synchronized-delay (CSD), such as a synchronous-mirror-delay (SMD) scheme, achieves fast lock of two clock cycles. However, conventional CSD suffers from bad resolution that is limited to a unit delay cell comprising inverters and narrow operating range.
To solve the resolution problem, several coarse-fine architectures adopting fine control methods have been proposed. However, they have a relatively long lock time due to a DLL loop or a digital sequential comparing operation to obtain digital codes.
In the proposed clock synchronization circuit, a fine CSD scheme is adopted to achieve the fast lock time and high resolution. The delay line in the fine CSD consists of the multi-path delay line based on the negative skewed delay technique.
By simulation and experiment, the fast lock and wide range operation are proved. The results show that the lock sequence is completed in a short clock cycle and the operation range is wide.
All the simulation and chip fabrication are based on the $0.18\mum$ CMOS process. The tested operation range is from 100MHz to 1GHz and lock time is 3 ~ 10 clock cycles. The power consumption is 55mW at 1GHz and the chip area is $0.21mm^2$.