(A) low noise digital phase-locked loop with quantization noise suppression and loop delay reduction techniques

Abstract

This paper introduces several techniques for DPLL in order to overcome the previous limitations, performance and portability. The DCO and PD resolution enhancement techniques and loop-delay reduction techniques are presented for lower phase noise, and a first fully synthesizable architecture is proposed for better portability of the DPLL. All the proposed techniques in the paper are verified in simulation and also, measurement results and detail abstracts for each technique are followings. Firstly, an LC tank based DCO with high frequency resolution by using a novel varactor bank is presented. The proposed varacter exploits the opposite C-V characteristics of the PMOS and NMOS and achieves unit capacitance that is an order of magnitude less than a simple PMOS or NMOS varactor. The simulation results show that the DCO achieves a frequency range of 4.5-5.5GHz while having 1.4kHz of minimum frequency step, which corresponds to 0.8aF of unit capacitance. A prototype DCO is designed in 65nm CMOS process, and achieves 50kHz of frequency resolution in measurement. Secondly, an oversampling PD by using the delay DCO clocks for the resolution improvement is proposed. The proposed PD oversamples the phase difference between the reference and DCO clock and hence, reduces quantization noise without high resolution delay cells. In simulation results, under -110dBc/Hz of in-band phase noise is achieved with about 100ps of delay cells resolution. A 2.1GHz digital fractional-N frequency synthesizer with the oversampling PD is fabricated in 90nm CMOS process and it has an active area of $0.3mm^2$. With the oversampling technique enabled, the measurement results show that the proposed DPLL achieves the reduced quantization noise level, while an additional delay cell noise degrades in-band phase noise. Thirdly, this paper analyzes the effect of loop delay on the wide-bandwidth DPLL and presents a technique for loop-delay reduction. In order to clarify the effect of loop delays on...