The current video signal processing requires the high processing capability and the large storage area. Thus, merging DRAM and logic into a single chip is inevitable to overcome the bottle-neck of data bandwidth between DRAM and logic in the high performance system. There are two trends in the design of merged DRAM logic(MDL), the general purpose MDL system and the dedicated processor. In general, a dedicated processor is not programmable and its application is limited and a general purpose MDL consumes too much area of silicon and is inefficient for video signal processing.
In this thesis, the optimization of data-paths in the programmable merged DRAM logic(MDL) for video signal processing is researched. The model of data-paths in the programmable MDL is generated and two basic measures are proposed through the analysis of the model. One is TRCC to check the number of clock cycles for the application and the other is DAR(DRAM Access Rate) to check the the synergy effect of MDL. TRCC represents clock cycles and should be minimized within the boundary of hardware resources. DAR indicates the ratio, clock cycles for data transfer over clock cycles for computation. An analysis of a digital video signal processing as an application is executed and TRCC is minimized by the multi-port SRAM and splittable processing units(ALU, MAC, and BS) within the limited area of silicon. DAR is determined so that the data bandwidth between DRAM and logic is not a bottle-neck of the performance of MDL system. The architecture of proposed data-paths shows the same performance with the dedicated MPEG2 decoder. The maximum data bandwidth between DRAM and logic is 6.4Gbytes/sec and the maximum processing capability for 8-bit video signal is 3.2GOPS with 200MHz clock frequency.