Optimal datapath design considering deep submicron interconnects = 심층 서브마이크론 인터커넥트를 고려한 데이타 경로 최적화

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dc.contributor.advisorKyung, Chong-Min-
dc.contributor.advisor경종민-
dc.contributor.authorYim, Joon-Seo-
dc.contributor.author임준서-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued1998-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=143483&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/36462-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1998.8, [ xi, 128 p. ]-
dc.description.abstractFor the high-speed, low power consumption, and small silicon area, the datapath has been designed by full custom approach in the commodity microprocessor chip. As the design complexity increases, the datapath compiler which generates the compact layout has been used both for ASIC and cost-performance microprocessor design to improve the design productivity. In this thesis, the new approaches and algorithms for the high-performance datapath compiler are proposed: such as placement, buffer sizing, interconnect design, track assignment, and layout schemes. To examine the performance of these approaches, ``real-world`` examples from the several complex microprocessors are used for the experiment. In determining the optimal datapath placement a hybrid approach of genetic algorithm(GA) and simulated annealing(SA)is applied to minimize both the track density and the wire length. To improve the computation speed, we utilize the good initial population generation heuristics and datapath-specific genetic operators. Experimental results show that our hybrid approach outperforms the existing genetic approaches and gives similar results to the simulated annealing using only 44% of the computation time of SA. The traditional datapath compiler generates the same-sized buffers for all bits. Considering the bit-by-bit difference of load capacitance in real designs, the bit-wise buffer sizing scheme is proposed. This scheme leads to the balance of the bit-wise delay and the power minimization. According to the experiments, the power consumption of the tri-state driver for the long running bus can be minimized as much as 43% by the bit-wise buffer sizing scheme. As the CMOS technology enters into deep submicron design era, the inter-wire cross-coupling effect gives large impact on the performance. The iterative interconnect sizing method considering the cross-coupling effect is suggested with experimental data based on 0.25μm technology. An effective control signal or...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectMicroprocessor-
dc.subjectDeep submicron-
dc.subjectInterconnect-
dc.subjectDatapath-
dc.subjectCAD-
dc.subject캐드-
dc.subject마이크로프로세서-
dc.subject심층 서브마이크론-
dc.subject인터커넥트-
dc.subject데이타패쓰-
dc.titleOptimal datapath design considering deep submicron interconnects = 심층 서브마이크론 인터커넥트를 고려한 데이타 경로 최적화-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN143483/325007-
dc.description.department한국과학기술원 : 전기및전자공학과, -
dc.identifier.uid000935299-
dc.contributor.localauthorKyung, Chong-Min-
dc.contributor.localauthor경종민-
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EE-Theses_Ph.D.(박사논문)
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