(A) VLSI architecture for HMM-based large-vocabulary speech recognitionHidden markov model을 이용한 대용량 음성인식을 위한 VLSI 구조

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Hidden Markov Model (HMM)-based algorithms have been used successfully in many speech recognition systems, especially in large vocabulary systems. Although general purpose processors can be employed for those systems, they inevitably suffer from the computational complexity and enormous data required in HMM. Therefore, it is desirable for real-time speech recognition to develop a specialized hardware to accelerate the recognition steps in HMM. In this dissertation, we develop a VLSI architecture which can expedite the HMM scoring steps for large vocabulary recognition systems. First, we examine the properties of HMM which can lead to a simple and efficient hardware structure. In HMM, most states are locally connected to only three of fewer preceding states and thus the number of states to be stored for later use is very small, and those irregular patterns of transitions between states make it inefficient to use the regular structures which have been developed for such as the Viterbi decoder and the ring-connected systolic array. In addition, we change the original Viterbi scoring algorithm into a logarithmically quantized version for finite precision hardware implementation and show experimental results on the effect of quantization. Second, with the properties of HMM and the logarithmic version of the Viterbi scoring algorithm, we propose a new and very simple processing element (PE) to be used in the scoring phase of HMM, which is modular and regular in structure. The complexity of managing the irregular transitions between states can be overcome by employing the elastic storage implemented by four pairs of multiplexers (MUXs) and D registers. The proposed PE is not customized to a particular HMM topology, which can incorporate various HMM topologies by modifying four 1-bit signals that control MUXs in the elastic storage. Third, we propose pipelining and parallel processing technique that can provide more throughput by employing multiple PEs in a 1-D or 2-D ...
Advisors
Kyung, Chong-MinresearcherLee, Hwang-Sooresearcher경종민researcher이황수researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
1994
Identifier
69056/325007 / 000875410
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 1994.2, [ xv, 118 p. ]

URI
http://hdl.handle.net/10203/36212
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=69056&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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