#### Two dimensional device simulation and characterization of GaAs floated electron channel field effect transistor = 갈륨비소 부동전자채널 전계효과 트랜지스터의 2차원 소자 시뮬레이션 및 특성분석

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dc.contributor.authorLee, Yoon-Jong-
dc.contributor.author이윤종-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued1994-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=69048&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/36204-
dc.description학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 1994.2, [ iv, 129 p. ]-
dc.description.abstractThe transconductance compression near subthreshold regime observed in GaAs Floated Electron Channel Field Effect Transistor (FECFET) is investigated by the electron flux profile extracted from the drain current versus gate voltage measurement in the saturation region of operation and two-dimensional device simulation. PISCES-2B and MEDICI are used for the two dimensional simulation. The applicability of the simulators for the simulation of GaAs MESFET is studied taking into account the velocity enhancement effect with reducing gate length. It is demonstrated that PISCES-2B and MEDICI can be well utilized for both DC and AC device simulation of state-of-art GaAs MESFET although they have some limits in describing the effect of velocity overshoot in submicrometer gate length GaAs MESFET. It is shown that the transconductance compression of GaAs FECFET is caused by electron pile-up near the top vertex of void due to the non-uniform profile of transport parameters in the region. The drift mobility profile of GaAs active layer on the top vertex is obtained by the simple etch-and-measure experiment for confirming the non-uniform profile of transport parameters near the top vertex of void. The process sensitivity of the device performance of FECFET is analyzed by using the device simulation when key structure parameters of FECFET are changed. It is shown from the analysis that the optimal vertical distance between the top vertex and the ohmic front of FECFET is about 0.2 $\mu$m. When the metallized gate length becomes decreased, the current-gain cut-off frequency of FECFET becomes increased following the linear relationship with the inverse of the gate length. As the gate length becomes reduced down to 0.3 $\mu$m, the effect of gate fringe capacitance becomes evident and thus the increase of the cut-off frequency is saturated. In addition, the important DC parameters such as threshold voltage and transconductance are more sensitive to gate displacement relative to cen...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.titleTwo dimensional device simulation and characterization of GaAs floated electron channel field effect transistor = 갈륨비소 부동전자채널 전계효과 트랜지스터의 2차원 소자 시뮬레이션 및 특성분석-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN69048/325007-
dc.description.department한국과학기술원 : 전기 및 전자공학과, -
dc.identifier.uid000845234-
dc.contributor.localauthorKwon, Young-Se-
dc.contributor.localauthor권영세-
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EE-Theses_Ph.D.(박사논문)
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