Simulation acceleration of transaction-level SoC design with RTL sub-blocks

Abstract

This paper presents a scheme called PrePack for suppressing the channel traffic between simulator and accelerator in the accelerator-based hardware/software co-emulation where the accelerator models some RTL sub-blocks while the simulator runs transaction-level model of the remaining part of the Design Under Verification (DUV). With conventional simulation accelerator, a cycle consisting of a pair of evaluations of simulator and accelerator occurs at every valid simulation time, which results in poor simulation performance due to the overhead of simulator-accelerator channel access often accounting for more than 99% of total channel traffic time. (Total channel traffic time consists of channel access time for arbitration/protocol exchange and pure data/signal transmission time.) The overhead due to channel access can be reduced by merging as many channel transactions on the channel as possible into a single burst traffic, which is achieved in this paper by `prediction and rollback.`` In the proposed `prediction and rollback`` scheme, one of the two verification do-mains, i.e., software simulation and hardware acceleration, leads the other while the leading domain predicts the states of the lagging domain. Therefore, the evaluation of simulator and accelerator no longer need to alternate at every simulation cycle. Under ideal condition with 100% prediction accuracy, PrePack has shown a 15x speedup compared to the conventional scheme. When applied to AES and JPEG example systems, PrePack showed performance gain of 8.7 and 2.9, respectively.