Accelerating multimedia applications with a reconfigurable system = 멀티미디어 프로그램 가속을 위한 재설정 가능 시스템에 관한 연구

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The verification time has become the most important issue on the de-signing a chip, especially on implementing an algorithm which requires large computation capacity, such like multimedia, on a chip. This pa-per is consisted of two parts: at first, the reconfigurable system which enables the algorithm runs with a target board and development environment which synthesize codes to connect the algorithm and interfaces of chips are introduced. The second one is the cosimulation environment within which the algorithm partitioned to hardware and software are verified step by step. The embedded software is executed on native machine-code level, instead of simulation on ISS(Instruction Set Simulator), while estimating cycle counts and synchronizing with the hardware models at basic block boundary. The proposed idea is validated by emulating a MP3 decoder chip with a public domain MP3 program and by simulating software and hardware models of the chip together with the proposed simulation environment.
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2002
Identifier
177323/325007 / 000955276
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2002.2, [ vi, 55, [6] p. ]

Keywords

Hardware/Software co-simulation; Emulation; System-on-a-Chip; 시스템온칩; 하드웨어 소프트웨어 동시검증; 하드웨어 에뮬레이션

URI
http://hdl.handle.net/10203/36028
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=177323&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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