(A) study on interface synthesis for system-on-a-chip design

Abstract

As the chip integration technology increases, a chip supports various functions. Currently, most part of the system function is integrated into a single chip. This complex chip is called System-On-Chip(SoC) which consists of three parts: the interface hardware blocks supporting various interface of the chip, hardware blocks accelerating the chip functions, and a processor block controlling the chip and running the software programs. Conventional design methodology requires long design cycle, since a design was started from the transistor level circuit design, although the time-to-market issue becomes one of most important issues. Thus, a new design methodology, so called, IP-based design methodology, is prevailing to design a new chip. The methodology is based on the reuse of well-designed and verified IPs. In this dissertation, a new interface hardware synthesis scheme is proposed to adapt to the IP-based design methodology. The proposed scheme considers various aspects to apply a real-world designs. Especially, if IPs operating at different frequencies are integrated into a single chip, an interface hardware block generation scheme is proposed to interface between IPs. The proposed scheme enables to achieve more efficient chip due to exploring various ready-made interface hardware blocks. Additionally, the proposed scheme can be applied to the interface hardware between IPs with different data width and is applied to a real system to prove the efficiency. A new hardware architecture is also proposed to reduce the hardware buffer which is a major hardware component of the interface hardware. The interface buffer is dynamically assigned to the various interface logics within a single chip, and the hardware usage is increased as compared with the statically assigned scheme. The proposed architecture is implemented in FPGA, the required area was reduced by 20%. Finally, the interface verification environment is designed to verify a designed interface hardware. A ...