DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Choong-Ki | - |
dc.contributor.advisor | 김충기 | - |
dc.contributor.author | Chung, Hoon-Ju | - |
dc.contributor.author | 정훈주 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2002 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=174631&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/35997 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2002.2, [ xi, 75 p. ] | - |
dc.description.abstract | In this dissertation, poly-Si TFT``s for low leakage current and analog buffers for data drivers of poly-Si TFT-LCD’s have been proposed. For low leakage current, dual-gate poly-Si TFT``s with intermediate lightly doped region (LDR) have been proposed. For analog buffers of integrated data driver, three analog buffers have been suggested - a push-pull analog buffer, a modified analog buffer, and a biased analog buffer. Dual-gate poly-Si TFT``s with intermediate lightly doped region have been developed for low leakage current. The main feature of dual-gate poly-Si TFT``s is a lightly doped region instead of a highly doped region at the active layer between the two gates. The proposed dual-gate Poly-Si TFT with LDR has a simple fabrication process and achieves symmetric structure with immunity to the misalignment induced by the lithographic process. To achieve symmetric structure in dual-gate poly-Si TFT with LDR, the maximum alignment margin is a quarter of the channel length ($L_ch$/4). We have demonstrated that the leakage current of the proposed poly-Si TFT is effectively reduced and becomes less dependent on $V_GS$ in high $V_DS$ region, since the LDR reduces the electric field near the drain while the ON current is slightly reduced due to the series resistance in the LDR. Moreover, the optimization of doping concentration of LDR has been proven to increase the ON/OFF current ratio. When the length of LDR is 2um and LDR implant dose is $2×10^13cm^{-2}$, the leakage current of dual-gate poly-Si TFT with LDR is reduced by about three orders of magnitude, compared to the single-gate poly-Si TFT, and the maximum ON/OFF current ratio is obtained. We have proposed new push-pull analog buffers for integrated data driver circuit of large-area poly-Si TFT-LCD``s. We have presented three new circuits for analog buffers. They are a push-pull analog buffer, a modified push-pull analog buffer, and a biased push-pull analog buffer with immunity to variations of poly-Si TF... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Poly-Si TFT-LCD | - |
dc.subject | Integrated Data Driver | - |
dc.subject | Analog Buffer | - |
dc.subject | 이중 게이트 다결정 실리콘 박막 트랜지스터 | - |
dc.subject | 저농도 도팅 영역 | - |
dc.subject | 다결정 실리콘 박막 트랜지스터 액정 표시기 | - |
dc.subject | 집적 데이터 구동회로 | - |
dc.subject | 아날로그 버퍼 | - |
dc.subject | Dual-Gate Poly-Si TFT | - |
dc.subject | Lightly Doped Region | - |
dc.title | Dual-gate poly-Si TFT's with intermediate lightly doped region and analog buffers for integrated data drivers of poly-Si TFT-LCD's | - |
dc.title.alternative | 중간에 저농도 도핑 영역을 갖는 이중 게이트 다결정 실리콘 박막 트랜지스터와 다결정 실리콘 박막 트랜지스터 액정 표시기의 집적 데이터 구동회로를 위한 아날로그 버퍼 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 174631/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 000975369 | - |
dc.contributor.localauthor | Kim, Choong-Ki | - |
dc.contributor.localauthor | 김충기 | - |
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