IP selection for system-on-a-chip design = 시스템칩 설계를 위한 IP 선택

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The huge number of transistors available in nowadays System-on-Chip (SoC) gives system designers both challenges and opportunities. The gap between silicon capacity and design productivity is still growing and threatening to slow down the growth of semiconductor industry. To reduce the gap, reusable building blocks (also known as Intellectual Property, or IP) would be extensively used so that more than 80% of a typical SoC design will be filled with IP``s in 2009. Therefore, there is a need for a framework that helps system designers decide whether each IP is selected or not, and synthesize an SoC architecture through trade-offs between various conflicting design constraints. Furthermore, the framework must exploit IP``s with imprecise design costs, e.g., imprecise area, energy consumption, execution time, design time, and design quality, because IP``s are developed in different companies with different design skills and technologies, with their details typically not available to the user before use. Even though the precise design costs of an IP are available, the design costs are different from those of the IP in various target environments of IP integrators because the provided design costs are obtained just in a development environment of an IP provider. In this thesis, we present an IP-based SoC synthesis framework focusing on how to select IP``s from different sources and how to integrate the selected IP``s using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IP``s with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted into an equivalent mixed integer linear programming (MILP) model without increasing the computational complexity. Then, the equivalent MILP model is solved to decide whether each IP is selected or not, and to locate the selected IP on the optimal on-chip bus of a hierarchical bus architecture that consists of on-chip buses with different bu...
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2002
Identifier
174618/325007 / 000965060
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2002.2, [ xi, 78, [9] p. ]

Keywords

Uncertainty; Possibilistic mixed integer linear programming; IP selection; System-on-Chip; 시스템칩; 불정확성; 퍼지선형모델링; IP선택방법론

URI
http://hdl.handle.net/10203/35985
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=174618&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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