(A) multilevel parallel texture cache memory using EML for 3D graphicsEML 을 이용한 3 차원 그래픽스용 다층 병렬 텍스쳐 캐쉬메모리

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As PC graphics applications such as 3D game and 3D advertisement require more realism, various advanced graphics algorithms are aggressively applied to PC graphics applications. Texture mapping is one of the most effective graphics operations to enhance the realism of 3D graphics scenes. However, it requires large bandwidth on the system bus, such as the AGP or PCI bus, for loading texture images from the system memory to a graphics card. Furthermore, as the number of graphics pipelines in the PC graphics card increases for high-speed parallel rendering, texture data distribution among the parallel graphics pipelines becomes an important issue. In this research, a new texture cache memory architecture, named multilevel parallel texture cache (MPTC), for both reducing the texture loading bandwidth and supporting parallel graphics pipelines more efficiently is proposed. The performance of the MPTC is analyzed on 3DOperaMC graphics simulation environment developed for this research. A prototype chip has been designed and implemented by using 0.16 um DRAM-based SOC technology. During the chip implementation, various circuit-level techniques to enhance the performance of the cache memory have been proposed and employed. For the chip testing and architecture validation, a graphics hardware system, named 3DTango, has also been developed. In this full research flow, the proposed cache architecture has been validated that it is effective in both reducing the required texture loading bandwidth on the system bus and supporting parallel graphics pipelines. The proposed cache architecture is composed of a large DRAM L2 cache memory, parallel SRAM L1 cache memories and integrated texture filtering modules based on trilinear interpolation. The large DRAM L2 cache memory (8 Mbytes) reduces the required texture loading bandwidth on the system bus by exploiting the inter-frame texture data access coherency between consecutive graphics frames. 3DOperaMC simulation results show th...
Advisors
Yoo, Hoi-Junresearcher유회준researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2002
Identifier
174600/325007 / 000975125
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2002.2, [ iv, 112 p. ]

Keywords

Memory; Texture Cache; 3D Graphics; EML; 캐쉬메모리; 텍스쳐; 3 차원 그래픽스; MDL

URI
http://hdl.handle.net/10203/35968
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=174600&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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