Fabrication, characterization, and performance enhancement of Si nanocrystal memory = 실리콘 나노 결정 메모리의 제작, 분석 및 성능향상

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dc.contributor.advisorLim, Koeng-Su-
dc.contributor.advisor임광수-
dc.contributor.authorBaik, Seung-Jae-
dc.contributor.author백승재-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2001-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=169571&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35956-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2001.8, [ iii, 117 p. ]-
dc.description.abstractMemory structure called nanocrystal memory or metal-oxide-semiconductor memory based on nanocrystal, is one of the floating gate memory structure that uses two-dimensional nanocrystal array as a floating gate material. For the potentially high performance as well as the process compatibility, it gets much attention around the semiconductor device engineers. In this thesis, investigation on the fabrication methods of nanocrystal array, characterization of the device mainly on discharging phenomena, and speculation as well as implementation of the highly reliable device structure is presented. Novel fabrication methods presented in this thesis are oxidation of microcrystalline Si film and deposition method by photo-chemical vapor deposition. They were adequate for fabrication of high-density small nanocrystal array. Especially, the deposition method produced 3nm-sized nanocrystal array with spatial density of $2\times10^{12}cm^{-2}$. It was verified that there are two origins for long retention time in nanocrystal memory employing ultrathin tunneling layer. One structural origin is due to the dot-to-dot isolation of nanocrystal array and the other physical origin is due to the presence of deep trapping center in nanocrystal. Metal-oxide-semiconductor field effect transistor based on oxidized microcrystalline Si/thin oxide gate structure, i.e., continuous floating gate material was investigated to clarify the reduced discharging from the nanocrystal floating gate. The charge retention time is estimated be smaller than 20ms. For the same tunnel oxide layer, nanocrystal memory based on nanocrystals exhibits far higher retention time. These results prove the drastic suppression of the discharging by employing collection of isolated storage sites as floating gate material, i.e., nanocrystal array. However, this structural reason cannot completely explain the charge retention characteristic of the nanocrystal memory; i.e., the assumption of deep trapping cent...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectasymmetrical tunneling layer-
dc.subjectamorphous carbon-
dc.subjectdischarging mechnism-
dc.subjectnanocrystal-
dc.subjectdeep trap level-
dc.subject깊은 포획 준위-
dc.subject비대칭 터널링 박막-
dc.subject비정질 탄소-
dc.subject방전 기작-
dc.subject나노결정-
dc.titleFabrication, characterization, and performance enhancement of Si nanocrystal memory = 실리콘 나노 결정 메모리의 제작, 분석 및 성능향상-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN169571/325007-
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid000965185-
dc.contributor.localauthorLim, Koeng-Su-
dc.contributor.localauthor임광수-
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EE-Theses_Ph.D.(박사논문)
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