Over GHz low-power RF clock distribution for a multi-processor digital system = 다중 프로세서 디지털 시스템을 위한 기가헤르쯔급 RF 클럭 분배

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Conventional digital clock distribution for a multiprocessor system using global clocking poses a severe power consumption problem for GHz clock distribution because of transmission line losses, and it poses difficult signal integrity problems due to clock skew, clock jitter, crosstalk, switching noise, and signal reflection. To overcome these conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. On the other hand, a salphasic clock distribution for minimizing clock skew using spatial phase properties of a standing wave has also been introduced to achieve lower design complexity and a more economical system than the conventional digital clock distribution. In the salphasic technology, a lossy transmission line does not exhibit purely salphasic behavior, and it is difficult to design a variety of distribution geometries for implementing tuning subregions. Recently, a wireless clock distribution has been proposed as an alternative interconnection system capable of distributing high frequency clock signals at the speed of light using microwave. However, this clocking scheme has very low system efficiency and occupies a lot of chip area due to a transmitting and a receiving antenna. Over GHz multiprocessor digital systems using global clocking requires a clock distribution technique seeking to achieve cost effectiveness and high-performance while minimizing power consumption, skew and jitter. This paper firstly proposes an RF clock distribution (RCD) scheme for high-speed digital applications, especially a multiprocessor computer system. The system comprises a RF clock transmitter as a clock generator, an H-tree with junction couplers as a clock distributing network and a RF receiver as a di...
Advisors
Kim, Joung-Horesearcher김정호researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2001
Identifier
169532/325007 / 000975098
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2001.8, [ xi, 141 p ]

Keywords

Signal Integrity; GHz Low-Power Clock Distribution; Multi-Processor Digital System; RF Clock Distribution; EMI; 신호 무결성; 다중 프로세서 디지털 시스템; 저전력 클럭 분배; 기가헤르쯔급 클럭 분배; RF 클럭 분배

URI
http://hdl.handle.net/10203/35946
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=169532&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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