Hot-carrier effects in BC-MOSDET and new CMOS logic circuits for high reliability

Abstract

Hot-carrier effects in buried-channel MOSFET``s (BC-MOSFET``s) and two new circuit design concepts for reducing hot-carrier problems in CMOS logics dramatically, are presented. The first part of the thesis is concerned with the substrate current, one of the hot-carrier effects, of buried-channel enhancement-mode n-MOSFET``s using a p-type polysilicon gate. Compared with the conventional MOSFET (surface-channel enhancement-mode n-MOSFET using an n-type polysilicon gate), this device shows higher breakdown voltage and reduced substrate current, even though the statid I-V characteristics in linear and saturation regions are almost identical. It is also found that the rate of transconductance degradation for a given substrate current is smaller in BC-MOSFET``s than in conventional MOSFET. In the second part of the thesis, two circuit design concepts for highly reliable CMOS logics without any change of device structure and/or fabrication process are proposed. The first method is called adjusting Gain factor Ratio (AGR) method and the second is called Self Bootstrapping Method (SBM). These two methods lower the channel electric field in n-MOSFET during switching transients, leading to the suppression of the substrate current. AGR scheme decreases the channel electric field which generates the hot carriers by shifting the transitiion point of the transfer characteristics of CMOS inverter from right to left. Experimental results show that the substract current is reduced by a factor of about 0.46 for the devices with the channel length of 2$\mu$m when the gain factor ratio is increased from 1 to 3. By computer simulations, the recommandable range in which AGR concept never results in the degradation of logic performances such as rise and fall time is presented. Meanwhile, is SBM scheme, experimental and simulation results show that about 3.9 times smaller peak substrate current is obtained in NAND logic circuits when compared with conventional NAND logic circuits. The...