Early in the VLSI design process, designers must make far reaching decisions based on incomplete or tentative information. The external interface of the cells that correspond to the constituents (size and shape of components and the positions of the pins) must sometimes be determined before the cells have been designed. Floorplanning consists of finding positions for the constituent components and determining constraints on external interfaces for the corresponding cells that have flexibility in their interface. That is, the floorplanning problem is concerned with the placement of rectangular cells of varying sizes and shapes such that the total area occupied by the cells and the interconnections is minimum. Floorplanning is related to placement, and many of the same techniques are used. However, the extra degree of freedom (the flexibility of the interfaces of the cells that comprise the design) significantly expands the size of the design space that must be exposed to component placement. In the physical design, due to the high complexity of the problem, most systems divide the physical design process into four steps: floorplanning, pin assignment, global routing and detailed routing. However, because these steps are very closed related to each other, these problems must be considered at same time. We propose a new floorplanning algorithm which handles a mixture of fixedshaped and flexible-shaped blocks in a chip aspect ratio within a given range combining the floorplanning step, the pin assignment step and global routing step. This algorithm consists of three stages. In the first stages, overlapped blocks in the initial placement obtained using FDR (Force Directed Relaxation) are spread out uniformly over the whole chip area using the so-called Ratioed Rectangular Voronoi Diagram such that each block finds enough space without significant overlap with its neighboring blocks. In the second stage, each block is reshaped or moved by the independent move of each...