DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Park, In-Cheol | - |
dc.contributor.advisor | 박인철 | - |
dc.contributor.author | Kim, Tae-Hwan | - |
dc.contributor.author | 김태환 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2010 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=455420&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/35605 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 2010.08, [ vii, 68 p. ] | - |
dc.description.abstract | MIMO spatial multiplexing is widely adopted in upcoming wireless communication standards to achieve high spectral efficiency. It virtually increases the channel capacity by employing multiple spatial streams associated with multiple antennas. The extended channel capacity can boost the throughput performance, but much complicated signal processing is required to cope with the multiplicity and interference among the spatial streams. In this research, several new algorithms and implementation techniques are proposed to achieve an efficient VLSI realization of symbol detectors for MIMO spatial multiplexing systems. The proposed ideas are validated by implementing two MIMO symbol detectors based on the proposed ideas. The first one is based on a K-best algorithm. To reduce the complexity required in tree-expansion and sorting, some children of a candidate are not expanded if they are estimated as inferior ones, and they are not considered in the sorting. An efficient pipeline scheduling called early forwarding is also proposed. The early forwarding technique enables registers to be shared between the pipeline stages, and minimizes the switching activities of registers, which results in a low-power and small-area implementation. Implemented using 0.18-$\mum$ CMOS technology, the proposed detector achieves 584 Mbps throughput, occupying $1.9mm^2$. Its energy consumption is 443 pJ/bit at 1.8V supply. The second one is based on a modified Dijkstra`s algorithm. The classical Dijkstra`s algorithm is modified to enable the overlapped processing of the tree-expansion and the sorting. Additionally, a simple $L^2$-norm approximation is proposed to reduce the computational complexity required in the tree-expansion. Implemented using 0.18-$\mum$ CMOS technology, the proposed detector occupies achieves up to 300 Mbps throughput, occupying $0.49mm^2$. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | VLSI | - |
dc.subject | Spatial multiplexing | - |
dc.subject | Sphere decoding | - |
dc.subject | Multi-input multi-output | - |
dc.subject | Processor | - |
dc.subject | 무선통신 | - |
dc.subject | 프로세서 | - |
dc.subject | 집적시스템 | - |
dc.subject | 스피어디코더 | - |
dc.subject | 다중입력 다중출력 시스템 | - |
dc.title | High-throughput and small-area sphere decoders for MIMO communication Systems | - |
dc.title.alternative | MIMO 통신 시스템을 위한 고성능 저면적의 스피어 디코더 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 455420/325007 | - |
dc.description.department | 한국과학기술원 : 전기 및 전자공학과, | - |
dc.identifier.uid | 020075046 | - |
dc.contributor.localauthor | Park, In-Cheol | - |
dc.contributor.localauthor | 박인철 | - |
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