(The) design of digital mismatch calibration circuitry for wideband CMOS direct-conversion receiver applications광대역 CMOS 직접 변환 수신기를 위한 디지털 부정합 보상회로의 설계

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This work presents a high-performance CMOS harmonic rejection mixer with digitally programmable mismatch calibration circuitry in direct-conversion architecture for ultra-wideband wireless applications such as terrestrial and cable digital TV (DTV) tuner. Among the technical challenges that DTV tuners with direct-conversion receiver architectures operating in the 48-862 MHz DTV frequency band face due to its ultra-wideband characteristics, harmonic mixing in the VHF band of 48-300 MHz between the input RF signal and the local oscillator harmonics is the most critical problem that must be solved. To obtain a harmonic rejection of over 60 dBc, which is the required specification in ATSC terrestrial and cable DTV standard, a harmonic rejection mixer with mismatch calibration circuitry is proposed. Conventional harmonic rejection mixers suffer from phase and/or gain mismatch and its harmonic rejection performance is severely degraded to 30 to 40 dBc, depending on the amount of mismatch. Also, process, voltage, and temperature (PVT) variations affect the consistency of the harmonic rejection performance. With the proposed simple mismatch calibration circuitry as well as the algorithm, both phase and gain mismatch can be compensated, thus consistently achieving a harmonic rejection of over 60 dBc without degrading other performance parameters of the harmonic rejection mixer such as power consumption, gain, noise figure, and linearity. To verify its harmonic rejection performance, a prototype direct-conversion receiver chip is implemented using single-poly six-metal 0.18um CMOS technology. Under normal operating conditions, the implemented harmonic rejection mixer with the mismatch calibration circuitry guarantees a measured 3rd-order harmonic rejection ratio of over 70 dBc. To test its robustness to PVT variations, the harmonic rejection ratio of over 20 samples of the fabricated chip is measured at temperature conditions at 0℃ and 60℃ and supply voltages at 1.7 ...
Advisors
Lee, Kwy-Roresearcher이귀로researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2009
Identifier
309325/325007  / 020037635
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2009.2, [ iii, 161 p. ]

Keywords

cmos; harmonic rejection mixer; calibration; direct conversion receiver; 씨모스; 하모닉 억제 믹서; 부정합 보상; 직접변환수신기; cmos; harmonic rejection mixer; calibration; direct conversion receiver; 씨모스; 하모닉 억제 믹서; 부정합 보상; 직접변환수신기

URI
http://hdl.handle.net/10203/35511
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=309325&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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