Temporal partitioning to amortize reconfiguration overhead for dynamically reconfigurable architectures = 동적 재구성 아키텍처의 재구성 오버헤드를 줄이기 위한 시간적 분할 기법

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In these days, many dynamically reconfigurable architectures have been introduced to fill the gap between ASICs and software-programmed processors such as GPPs and DSPs. These reconfigurable architectures have shown to achieve higher performance compared to software-programmed processors. However, the current reconfigurable architectures suffer from a significant reconfiguration overhead so that it severely degrade the overall performance of reconfigurable architectures. In order to deal with this reconfigurable verhead, there had been intensive research on hardware and software techniques such as configuration compression, configuration prefetching, configuration sharing, multi-context switching, and partial reconfiguration. Among these techniques, many commercial and academic reconfigurable architectures provide the partial reconfiguration. When compiling applications written in high-level languages for these reconfigurable architectures with partial reconfiguration, compilers or synthesis tools should split into the temporal partitions using temporal partitioning. And then, each temporal partition is executed on these reconfigurable architectures through three stages: fetch, configuration, and computation. Therefore, it is important to split applications overlapping of the execution stages on different temporal partitions such that the reconfiguration overheads are minimized. In this dissertation, the temporal partitioning methodology are introduced to cope with partial reconfiguration. The proposed temporal partitioning methodology splits the application into several temporal partitions such that the reconfiguration overhead of each temporal partition can be overlapped with a computation time of the previous temporal partition. Therefore, the proposed temporal partitioning are able to amortize the reconfiguration overhead at high-level synthesis phase or compilation time. Also, temporal partitions inside a loop can be locally iterated by using a intra-...
Advisors
Kim, Tag-Gonresearcher김탁곤researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2008
Identifier
303625/325007  / 020025827
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2008. 8., [ vii, 76 p. ]

Keywords

Partitioning; Temporal Partitioning; Compiler; High-level synthesis; reconfigurable architecture; 컴파일러; 분할기법; 재구성 아키텍처; 동적 재구성 아키텍처; Partitioning; Temporal Partitioning; Compiler; High-level synthesis; reconfigurable architecture; 컴파일러; 분할기법; 재구성 아키텍처; 동적 재구성 아키텍처

URI
http://hdl.handle.net/10203/35477
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=303625&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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