Pixel-Level characterization and optimization of CMOS image sensor in low-voltage operation저전압 CMOS 이미지 센서에 대한 픽셀 레벨의 특성화 및 최적화

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dc.contributor.advisorHong, Song-Cheol-
dc.contributor.advisor홍성철-
dc.contributor.authorMheen, Bong-Ki-
dc.contributor.author민봉기-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2006-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=258152&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35383-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2006.8, [ xiii, 167 p. ]-
dc.description.abstractThe significant increase of market demands for low-cost and high-performance CMOS image sensor makes the development of CMOS image sensor more aggressive. However, lots of bottlenecks start to be found at optics and electronic systems recently. Most of all, recent degraded pixel performance in low voltage operation is one of the most intricate problems. Especially, as sub-0.18um CMOS process is adopted, the supply voltage is reduced less than 2.5V, which inevitably opens the possibility of incomplete reset of PPD, because the photodiode reset voltage, i.e., the pinning voltage $(V_{pin})$ can not be accordingly reduced. Furthermore, the potential barrier which exists between photodiode and charge transfer (TX) transistor due to surface implantation on top of the pinned photodiode (PPD) should be designed to be suppressed during reset and charge transfer operation. However, it is not easily obtained anymore due to the reduced operational voltage margin between the $V_{pin}$ and the floating diffusion (FD) voltage. Under these circumstances, prior to the introduction of non fully-depleted pinned photodiode (NFD-PPD), we first propose DC and noise setup as a cost-effective inspection tool in which a pixel-level characterization can be conducted using an external ADC board (Gage 1610 model). Using photodiode programming in the developed DC and noise setup, various performance parameters are extracted from a single pixel test pattern including dark current, $V_{pin}$, well capacity, the FD capacitance (conversion gain), the ratio of the PD capacitance over the FD capacitance, dynamic range, charge transfer curve, photon transfer curve and so on. The input-referred noise levels due to the used external ADC board and overall measurement setup are also experimentally measured, which verifies that the measured noise level, for example in PTC curves, is sufficiently lowered and not affected in the measurements. The measured minimum input-referred noise voltage power l...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectdevice scaling-
dc.subjectpinning voltage-
dc.subjectpinned photodiode (PPD)-
dc.subjectfour-transistor structure-
dc.subjectCMOS image sensor-
dc.subjectnon full-depleted pinned photodiode (NFD-PPD)-
dc.subject전압 스케일링-
dc.subject소자 스케일링-
dc.subject피닝 전압-
dc.subject핀드 포토다이오드-
dc.subject4-트랜지스터 구조-
dc.subject씨모스 이미지 센서-
dc.titlePixel-Level characterization and optimization of CMOS image sensor in low-voltage operation-
dc.title.alternative저전압 CMOS 이미지 센서에 대한 픽셀 레벨의 특성화 및 최적화-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN258152/325007 -
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid020025110-
dc.contributor.localauthorHong, Song-Cheol-
dc.contributor.localauthor홍성철-
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EE-Theses_Ph.D.(박사논문)
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