Energy-efficient CMOS frequency synthesizer architecture for low-power narrow-band wireless communication systems = 저전력 협대역 무선통신 시스템을 위한 고에너지 효율의 CMOS 주파수 합성기 구조

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Two implementation issues for a distributed LR-WPAN device, specified for a 2.4GHz ZigBee application, have been introduced. The first issue is the reduction of frequency settling time of a frequency synthesizer, which dominates the excessive active time duration for TDD switching between Tx-mode and Rx-mode and for the channel switching. In stead of adapting or widening the loop-bandwidth of the synthesizer, a two-point channel control architecture has been proposed to achieve short settling time even with an integer-N synthesizer, which has relatively narrow bandwidth and low active power consumption compared to a fractional-N one. The two-point channel control scheme is composed of main-path and compensation-path controls. While the main-path is the same as that of a conventional PLL, a DAC with tunable gain is used to directly control the linearized VCO for the compensation-path. We have achieved the settling time of near zero sec for the maximum 75MHz frequency jumping from 2.4GHz, which is specified by the standard, with the use of an integer-N architecture with narrow 20kHz loop-bandwidth. In addition, the fast-settling synthesizer has utilized a Vertical-NPN parasitic transistor, which is available in a conventional triple-well CMOS process, for the $1/f$ noise sensitive VCO biasing, and thereby the close-in phase-noise performance can be improved. Compared to the case of MOS transistor biasing, the close-in phase-noise was improved by 5dB with the same active power consumption. For the high frequency divider circuits, a low-voltage modified-TSPC circuit topology with only 2-transistor stacks has been proposed. By adapting the modified-TSPC topology for the high-frequency divider circuits, under lowered supply voltage of 1.2V, the power consumption was significantly reduced. When the phase-noise at 1MHz offset from 2.4GHz output frequency is -116.6 dBc/Hz, the total power consumption of the fast-settling synthesizer using 0.18$\\mu$m CMOS technology i...
Lee, Kwy-roresearcher이귀로researcher
한국과학기술원 : 전기및전자공학전공,
Issue Date
298976/325007  / 020025158

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2007.2, [ xi, 110 p. ]


Low-power; energy efficiency; frequency synthesizer; frequency offset; Time-to-Digital Converter (TDC); ZigBee; 저전력; 에너지 효율; 주파수 합성기; 주파수 오프셋; TDC; ZigBee; Low-power; energy efficiency; frequency synthesizer; frequency offset; Time-to-Digital Converter (TDC); ZigBee; 저전력; 에너지 효율; 주파수 합성기; 주파수 오프셋; TDC; ZigBee

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