Jitter-tolerant I/O clock distribution network using chip and package hybrid interconnection = 칩과 패키지의 혼성 전송선을 이용한 저 지터 입출력 클럭 신호 분배의 설계 및 구현

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As the clock frequency of digital systems goes higher up to multi-GHz, it is getting more important to distribute a clock signal to each destination with minimum timing jitter as not to exceed the timing margin of the system. Usually, a series of cascaded repeaters is indispensable to distribute a clock signal on a chip due to the lossy characteristic of on-chip global interconnection lines. The repeaters cause timing jitter on the clock signal when they are affected by power supply noise which is usually generated by digital logic core operations. Moreover, the number of repeaters required to distribute a clock signal is rapidly increasing as the clock frequency of the system goes higher. This thesis shows a conceivable solution called a chip-package hybrid clock scheme by which most repeaters are no longer necessary to distribute the clock signal on a chip. Since the repeater-free hybrid clock distribution network is robust for on-chip power supply noise, the simultaneous switching noise (SSN) generated by digital logic circuits on a chip affects little on the hybrid clock signal. The effects of off-chip power supply noise are also considered by categorizing them into two mechanisms called generation and propagation. The generation of the power supply noise is controlled by a self impedance lowering technique using both off-chip and on-chip de-coupling capacitors. And the propagation of the power supply noise is controlled by adopting an electromagnetic band gap (EBG) structure between a noise source and a victim. All results have been verified using both simulations and measurements and the chip-package hybrid clock network has shown dramatically reduced clock jitter compared to a conventional repeater-based clock distribution network.
Advisors
Kim, Joung-Horesearcher김정호researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2006
Identifier
258143/325007  / 020025875
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2006.8, [ viii, 104, [6] p. ]

Keywords

Interconnection; Jitter; Clock; Chip Package Hybrid; 칩 패키지 혼성모드; 전송선; 지터; 클럭

URI
http://hdl.handle.net/10203/35364
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=258143&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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