Trace-driven performance simulation modeling for fast evaluation of multimedia processor by simulation reuse

Abstract

Embedded systems market is rapidly growing due to the increasing need for product personalization, rapid growth of non-computing domains such as medical instrumentation and imaging, information appliances. Besides, the development of semiconductor technology enables us to integrate various forms of the chip. Due to this variety, hardware designer can consider various architectures which are made of various combinations of functional units and hardware parameters. Design space exploration of an optimal processor is a struggling job due to large design space. What is worse, the performance of simulators currently used to evaluate performance is very low since they intend to capture all behaviors of the hardware. Therefore, fast evaluation methodology for architecture without sacrifice of accuracy is crucial. This thesis proposes a rapid and accurate evaluation scheme for cycle counts and power consumption of a pipelined processor using simulation reuse technique. When we explore the optimal design in the design space, it is redundant to verify the functional correctness at each time when we evaluate a candidate design. Therefore, we introduce the performance simulation model for processor architecture which can evaluate the performance without considering the functional correctness. This model has an F5M-like form and can afford to take all hazard types of pipelined architectures into consideration. An application program, especially multimedia application, has much-iterative loops in general. This property invokes many iterative operations in the simulation. Our proposed evaluation method focuses on alleviating the iterative operations of conventional simulators in the loop. A performance simulator for the pipeline architecture has been developed through which greater speedup has been made compared with other approaches in the evaluation of cycle counts.