Cost-optimized system-on-chip implementation with on-chip network

Abstract

The VLSI technology evolution has driven system-on-chip (SoC) to have more communication-centric architecture than ever before. In order to cope with such complicated on-chip interconnect, Bus architecture is being replaced by On-chip Network (OCN) which has been researched actively recently. The most fundamental fact differentiating an OCN from legacy network architectures is that the OCN is implemented on silicon area. Therefore, an OCN research must be based on implementation issues while touching network-related problems. However, most of previous works take top-down approach in which legacy network architectures are shrunk to fit into on-chip situation, thus, the works lack considerations on implementation. In this paper, an OCN architecture is defined and cost-optimized for cost-effective operation and realization. Topology selection, channel width determination, packet format, and protocol definitions are studied based on actual implementation data. On-chip serialization technique is proposed to reduce overall network area and energy-consumption. For more practical use of the OCN, one of critical barriers in the OCNs of previous works, i.e. high end-to-end latency problem, is solved using a new global arbitration mechanism. Circuit innovation in on-chip serializer/deserializer achieves high-speed serialization up to 3Gb/s, reducing power-consumption as well as system overhead compared to conventional serdes``s. Adaptive bandwidth control scheme realizes dynamic trade-off between bandwidth and energy-consumption of links. An efficient synchronization method is also proposed considering the OCN characteristics. Through two OCN chip implementations using 0.38㎛ and 0.18㎛ CMOS technologies, feasibility of the network architectures of this work is demonstrated, and successful operations of the innovative circuit schemes are confirmed.