(An) efficient memory interface design based on access pattern analysis for SoC-based 3D graphics accelerator

Abstract

In these days, 3D graphics applications are extended to the mobile devices such as laptop, PDA, cellular phone, and so on. For these mobile devices, an SoC-based design methodology is employed for smaller area and fast development. Since the application specific functional units are offered as black boxed IPs for the SoC-based design, the IPs cannot be modified. Therefore, a new design guideline for SoC-based 3D graphics system without IP modification is required for performance enhancement and energy reduction. 3D graphics is an extremely memory dependent system. 3D graphics accelerator requires a local memory for frame buffer composed of a depth buffer and color buffer. For each pixel, several memory accesses are generated to the frame buffer. Since the growth speed of the memory performance cannot follow up that of the computing power of the 3D graphics accelerator, the memory access speed is the most important performance bottleneck for current 3D graphics acceleration system. Moreover, since the memory system is a dominant energy consuming part in 3D graphics system, the energy consumption of the local memory occupies a large part of that of the overall system. Therefore, an optimal memory system design method on the SoC-based design environment may enhance the performance and reduce the energy consumption of the 3D graphics acceleration system. Although a memory system design methodology based on the algorithm level access pattern analysis is very powerful and popular, this method cannot be applied to the 3D graphics due to some restrictions of the 3D graphics algorithm. In this thesis, instead of the algorithm level access pattern analysis, an architecture level analysis of the frame buffer access pattern of the recent 3D graphics accelerators that utilize multiple pipelined .rendering engines is proposed. Based on this analysis, I propose an efficient memory assignment method and access scheduling method of the concurrent memory accesses. The performanc...