Discrete event model verification methodology using system morphism시스템 사상성을 이용한 이산사건 모델 검증 방법론

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 403
  • Download : 0
DC FieldValueLanguage
dc.contributor.advisorKim, Tag-Gon-
dc.contributor.advisor김탁곤-
dc.contributor.authorHong, Ki-Jung-
dc.contributor.author홍기정-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2005-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=244912&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35287-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2005.2, [ vii, 90 p. ]-
dc.description.abstractModel verification examines the correctness of a model implementation with respect to a model specification. The model specification describes not only behavioral but also structural properties of a real system to be modeled. While described from model specification, implementation prepares to execute and evaluate a simulation model. Therefore, various implementation test methods have been evaluated for several years, especially within protocol conformance test and software test. Simulation model verification is experimented among various implementation tests. While former studies have merely focused on finite state machine(FSM), a simulation model usually consists of structural and behavioral properties with time constraints and finite states. However, it is difficult and complex to ensure the correctness of such a time constrained finite state implementation. In order to overcome the complexity of the problem, this paper presents a new method that provides the time constrained simulation model verification. The objective of this verification is to inspect the ways in which implementation satisfies specification at I/O level, not verifying whether implementation works exactly the same as specification. Implementation has I/O function level system morphism from specification, i.e., implementation accepts all possible I/O sequences that specification specifies. Timed state reachability graph(TSRG) is devised to generate all possible I/O sequences from a given DES model. Time complexity of all possible I/O sequences is too high to apply in practical test. To solve such time complexity, this paper proposes a method to reduce the redundancy of all possible I/O sequences, called a test I/O sequences set. Model verification can find all implementation faults by using the test set under the assumption that the maximum state size of the test target can be known. This assumption helps to find faults of the test target in a practical time bound. Time complexity of the pr...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectDEVSpecL-
dc.subjectTimed State Reachability Graph-
dc.subjectSystem Morphism-
dc.subjectModel Verification-
dc.subjectDiscrete Event System-
dc.subjectWeak Synchronization-
dc.subject약한 동기화v 동기화 가능성-
dc.subjectDEVSpecL-
dc.subject시간상태도달 그래프-
dc.subject시스템 사상성-
dc.subject모델검증-
dc.subject이산사건시스템-
dc.subjectSynchronization Feasibility-
dc.titleDiscrete event model verification methodology using system morphism-
dc.title.alternative시스템 사상성을 이용한 이산사건 모델 검증 방법론-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN244912/325007 -
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid000975423-
dc.contributor.localauthorKim, Tag-Gon-
dc.contributor.localauthor김탁곤-
Appears in Collection
EE-Theses_Ph.D.(박사논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0