Discrete event model verification methodology using system morphism = 시스템 사상성을 이용한 이산사건 모델 검증 방법론

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Model verification examines the correctness of a model implementation with respect to a model specification. The model specification describes not only behavioral but also structural properties of a real system to be modeled. While described from model specification, implementation prepares to execute and evaluate a simulation model. Therefore, various implementation test methods have been evaluated for several years, especially within protocol conformance test and software test. Simulation model verification is experimented among various implementation tests. While former studies have merely focused on finite state machine(FSM), a simulation model usually consists of structural and behavioral properties with time constraints and finite states. However, it is difficult and complex to ensure the correctness of such a time constrained finite state implementation. In order to overcome the complexity of the problem, this paper presents a new method that provides the time constrained simulation model verification. The objective of this verification is to inspect the ways in which implementation satisfies specification at I/O level, not verifying whether implementation works exactly the same as specification. Implementation has I/O function level system morphism from specification, i.e., implementation accepts all possible I/O sequences that specification specifies. Timed state reachability graph(TSRG) is devised to generate all possible I/O sequences from a given DES model. Time complexity of all possible I/O sequences is too high to apply in practical test. To solve such time complexity, this paper proposes a method to reduce the redundancy of all possible I/O sequences, called a test I/O sequences set. Model verification can find all implementation faults by using the test set under the assumption that the maximum state size of the test target can be known. This assumption helps to find faults of the test target in a practical time bound. Time complexity of the pr...
Advisors
Kim, Tag-Gonresearcher김탁곤researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2005
Identifier
244912/325007  / 000975423
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2005.2, [ vii, 90 p. ]

Keywords

DEVSpecL; Timed State Reachability Graph; System Morphism; Model Verification; Discrete Event System; Weak Synchronization; 약한 동기화v 동기화 가능성; DEVSpecL; 시간상태도달 그래프; 시스템 사상성; 모델검증; 이산사건시스템; Synchronization Feasibility

URI
http://hdl.handle.net/10203/35287
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=244912&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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