Optimization of low power CMOS RF receiver front-end design

Abstract

With the help of speedy scaling, CMOS starts to conquer the market of wireless SOC (System on a Chip) where power consumption is one of the most important issues. However, with respect to RF and analog design, scaling has not only bright side, e.g. NF gets better with scaling but linearity which is directly related with power consumption scales adversely. Thus, linearity optimization will be major issue in low power CMOS receiver with the start of never-ending scaling. This thesis is mainly focused on the linearization of CMOS RF circuits. First, highly linear CMOS RF front-ends, LNA and mixer circuits adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistor in parallel (multiple gated transistor, MGTR), combined with some additional circuit techniques such as cascode for amplifier and harmonic tuned load mixer, are reported. Experimental results show IP3 improvements at given power consumption by as large as 10 dB for the LNA at 900-MHz and 7 dB for the Gilbert cell mixer at 2.4-GHz without sacrificing other features such as gain and NF. Second, starting from investigating the behaviors of basic two differential circuits, such as fully differential amplifier and pseudo differential amplifier, a Differential MGTR (DMGTR) is newly proposed to improve the linearity (IIP3) of differential circuit without loss of differential benefits and other RF characteristics. Compared with conventional design approach, this design improves the IIP3 of 13 dB at similar CMRR, gain, and NF at negligible extra power consumption. With the DMGTR technique and other newly proposed programmable gain amplifier architectures, RF digitally Programmable Gain Amplifiers (RFPGA) for various mobile digital TV applications are designed. Measurement results of the UHF band RFPGA show NF of 4.5 dB, gain of 27 dB, and gain range of as large as 55 dB with 0.25dB resolution.