Design of CMOS receiver front-end for wireless communications

Abstract

This work describes the design methodology for highly-integrated wireless receiver front-end. As an design example, a fully integrated RF front-end for W-CDMA applications including a low noise amplifier, a downconversion mixer, a digitally programmable gain amplifier, a low-pass filter, an on-chip VCO, and a fractional-N frequency synthesizer is demonstrated using a 0.35-㎛ CMOS process. The measured phase noise of the on-chip VCO is -134 dBc/Hz at 1 MHz offset. The receiver RF front-end achieves a NF of 3.5 dB, an IIP3 of -16 dBm, and a maximum gain of 80 dB. The receiver consumes 52 mA with a 3-V supply and occupies only 2㎟ die area with minimal external components. To generate precise I/Q signals, self-calibration technique for I/Q phase mismatch is proposed. A 5-GHz LC quadrature VCO with calibration loop and a frequency synthesizer utilized in 5-GHz band wireless LAN, especially IEEE 802.11a, is designed using a 0.18-㎛ CMOS process to verify the functionality of the proposed scheme. The phase error after calibration is under 2-degree in serious device mismatch.