Design of CMOS receiver front-end for wireless communications = 무선 통신을 위한 CMOS 수신단의 설계

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This work describes the design methodology for highly-integrated wireless receiver front-end. As an design example, a fully integrated RF front-end for W-CDMA applications including a low noise amplifier, a downconversion mixer, a digitally programmable gain amplifier, a low-pass filter, an on-chip VCO, and a fractional-N frequency synthesizer is demonstrated using a 0.35-㎛ CMOS process. The measured phase noise of the on-chip VCO is -134 dBc/Hz at 1 MHz offset. The receiver RF front-end achieves a NF of 3.5 dB, an IIP3 of -16 dBm, and a maximum gain of 80 dB. The receiver consumes 52 mA with a 3-V supply and occupies only 2㎟ die area with minimal external components. To generate precise I/Q signals, self-calibration technique for I/Q phase mismatch is proposed. A 5-GHz LC quadrature VCO with calibration loop and a frequency synthesizer utilized in 5-GHz band wireless LAN, especially IEEE 802.11a, is designed using a 0.18-㎛ CMOS process to verify the functionality of the proposed scheme. The phase error after calibration is under 2-degree in serious device mismatch.
Advisors
Kim, Beom-SupresearcherPark, In-Cheolresearcher김범섭researcher박인철researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2004
Identifier
237647/325007  / 020005828
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2004.2, [ [vii], 120 p. ]

Keywords

LNA; MIXER; CLOCK GENERATOR; 아날로그 씨모스 회로; 수신단; 저잡음증폭기; 하향변환기; 클럭 생성기; ANALOG CMOS CIRCUIT; RECEIVER

URI
http://hdl.handle.net/10203/35217
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=237647&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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