DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Lee, Kwy-Ro | - |
dc.contributor.advisor | 이귀로 | - |
dc.contributor.author | Kim, Jin-Bong | - |
dc.contributor.author | 김진봉 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2004 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=237634&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/35204 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2004.2, [ xi, 128 p. ] | - |
dc.description.abstract | As the CMOS volatile memory (SRAM or DRAM) technology is improved, many types of high-density memory cell repair methods have been introduced. These are laser fusing, electrical poly fusing, ONO antifuse, CMOS antifuse and so on. Poly and metal fusing with laser instruments have widely been used in most of the memory manufacturers``. These, however, are not only very expensive, but have a limitation that they can only be done on wafer test, and that they are impossible to use at final test after packaging. Antifuse based on anti-fusing thin oxide between two electrodes has more reliable pre-/post-breakdown characteristics and has been adopted successfully in some commercial circuits, that is, the via antifuse used in the field programmable gate array (FPGA) from Actel, and the oxide-nitride-oxide (ONO) antifuse in DRAM from Hynix. But they are not directly applicable to standard CMOS products because of their incompatibility with standard CMOS process technology. In this thesis, I propose novel CMOS antifuse one-time programmable (OTP) ROM structure which is fully compatible with standard CMOS process and its application circuit, named, the 3-transistor cell CMOS OTP ROM array. The 3-T cell CMOS OTP ROM array is composed of only three nMOS``s. They are an nMOS antifuse, a high-voltage blocking nMOS and a cell access transistor. And this cell occupies very small chip area per 1-bit $(<10\mu^2 \MVAT ANAM 0.18\mu technology)$. The CMOS OTP ROM array using the antifuse based on permanent breakdown of MOSFET gate oxide is fabricated and characterized with several standard CMOS processes such as TSMC 0.18㎛, ANAM 0.18㎛ and ANAM 0.25㎛ process technologies. Most of all, the 64-kb OTP ROM, which is fabricated with ANAM 0.18㎛ process, its measurement results show that the 3-T OTP ROM structure is well applicable to high-density embedded program ROM for micro-controller units, one-time programmable configuration memory for FPGA, and several types of embedded memory... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | GATE-OXIDE BREAKDOWN | - |
dc.subject | CMOS OTP | - |
dc.subject | PROGRAMMABLE ROM | - |
dc.subject | CMOS ANTIFUSE | - |
dc.subject | CMOS ROM | - |
dc.subject | 씨모스 롬 | - |
dc.subject | 게이트 절연 파괴 | - |
dc.subject | 씨모스 오티피 | - |
dc.subject | 프로그래머블 롬 | - |
dc.subject | 씨모스 안티퓨즈 | - |
dc.title | Antifuse OTP ROM and tunneling EEPROM using single-poly standard CMOS process | - |
dc.title.alternative | 단일 폴리 표준 CMOS 공정을 사용한 안티퓨즈 OTP ROM 과 터널링 EEPROM | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 237634/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 000995099 | - |
dc.contributor.localauthor | Lee, Kwy-Ro | - |
dc.contributor.localauthor | 이귀로 | - |
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