Low-noise design methodology for CMOS integrated clock generation circuits = CMOS 집적 클럭 발생 회로들에 대한 저 잡음 설계 방법론

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Low-noise design methodology of clock generators in this thesis is to optimize their noise performance through circuit analyses or to propose new architectures when the noise characteristic is limited by other requirements from applications. Three kinds of clock generators such as a delay-locked loop (DLL), a voltage-controlled oscillator (VCO), and a frequency synthesizer, are designed and verified through chip fabrications in common CMOS processes. A mixed DLL is proposed to accommodate only advantages of an analog DLL and a digital DLL, and it is verified through the experiment results to have not only low jitter, but also low power and fast lock time. In order to improve the phase noise that is degraded by the integration of a VCO, a LC-ring structure is proposed as an architecture approach, and the noise enhancement effects are verified by noise analyses and experimental results. Finally, a frequency synthesizer is optimally designed to improve the in-band phase noise, and fully integrated using the proposed LC-ring oscillator. The result noise characteristic is shown to meet most wireless standard specifications.
Advisors
Kim, Beom-Supresearcher김범섭researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2003
Identifier
181163/325007 / 000985084
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2003.2, [ v, 109 p. ]

Keywords

VCO; DLL; PLL; Clock Generation Circuits; Frequency Synthesizer; 주파수 합성기; 공진 회로; DLL; PLL; 클럭 발생 회로

URI
http://hdl.handle.net/10203/35150
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=181163&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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