Design of a fault-tolerant bit-silced processor system

Abstract

For a bit-sliced processor system to tolerate module (or slice) failures, the module interconnection is very important. Interconnection structure must be regular because of the property of the bit-sliced system. Switching the faulty modules can be done by the mechanism which selectively activates and deactivates interconnections between modules by the control of the switching control unit. In order to tolerate any failure this paper proposes the generalized basic module and its application to the generalized distributed reconfiguration scheme. Generalized distributed reconfiguration scheme improves the shortingcomings of the distributed reconfiguration scheme. It is applied to the bit-sliced modular system which has an array structure. The reliability improvement of the generalized distributed reconfiguration scheme over the distributed reconfiguration scheme is confirmed by the computation of the MTTF. An architecture of the fault-tolerant bit-sliced processor system is proposed.