Parallelization and vectorization of irregular reductions on multicores with explicitly managed memory hierarchies명시적 관리 메모리를 가진 멀티코어를 위한 비정규 리덕션의 병렬화 및 벡터화

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Irregular reduction is one of the important computation patterns in the scientific application such as computer-based simulations for fluid dynamics or molecular dynamics. An effective compilation framework for parallelizing irregular reductions on high performance architectures is therefore important for the future computational science. Meanwhile, explicitly managed memory hierarchies have been proposed in the design of many-core processors. When hundreds or thousands of cores are embedded within one chip, software controlled memory hierarchies are particularly necessary to build scalable processor architectures. The irregularity in data accesses patterns presents several challenges for programmers to exploit those architectures. Managing memory hierarchy in software requires a lot of programming efforts and tends to be error-prone. The difficulties are even worse for applications with irregular data access patterns. Another problem caused by the irregular accesses is that they hinder the extraction of data-level parallelism for fine-grained parallel functional units such as multimedia extensions. The lack of effective analysis for irregular accesses limits the optimization opportunity for both compilers and moderate programmers. In this work, we propose a compilation framework for parallelizing irregular reduction on architectures with explicitly managed memory hierarchy. To relieve the burden of memory management from programmers, we develop a work-sharing construct for structuring parallel tasks, mapping the parallel tasks to processing units and scheduling data transfers between the memory hierarchies. A vectorization technique is also presented to address the challenges arose in the presence of array indirection, such as disjoint memory references, unknown alignment, dependence cycles, etc. We experimentally evaluate the effectiveness of our techniques for several irregular reduction kernels on the Cell processor embedded in a Sony PlayStation3. The r...
Advisors
Choe, Kwang-Mooresearcher최광무researcher
Description
한국과학기술원 : 전산학과,
Publisher
한국과학기술원
Issue Date
2010
Identifier
455440/325007  / 020047089
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전산학과, 2010.08, [ vii, 76 p. ]

Keywords

Compiler; Vectorization; Parallelization; Irregular Reduction; 비정규 리덕션; 컴파일러; 벡터화; 병렬화

URI
http://hdl.handle.net/10203/33312
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=455440&flag=dissertation
Appears in Collection
CS-Theses_Ph.D.(박사논문)
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