(A) static analysis framework with explicit synchronization for definite error detection on esterel = 명료한 동기화와 명확한 오류 검출을 위한 Esterel의 정적분석 기반구조

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Esterel is an imperative synchronous language with the perfect synchrony hypothesis which divides time into a sequence of logical time units. Esterel is well-adapted to develop control-dominant reactive systems. It is because imperative features of Esterel on the synchrony hypothesis help to control synchronization and preemption among threads that are executed simultaneously. However, it is hard to compute exact synchronization process and interferences among threads from Esterel programs, and this makes it difficult to analyze or diagnose the programs. In this thesis, we propose a new control flow graph (CFG) and a new logical semantics of Esterel that focus on exposing the synchronization process and implicit interferences among threads. First, we present an over-approximated CFG of an Esterel program. Simple and convenient CFGs can help to analyze Esterel programs or to detect errors from the programs. Regardless of imperative features of Esterel, combination of parallel execution and preemption causes implicit interferences between threads, and they make it difficult to build CFGs of Esterel programs. Previous researches are not suitable for CFG-based static analyses of Esterel, because they focus on compilation or simulation of Esterel programs. We develop a new method to construct over-approximate CFGs of Esterel programs that expose invisible interferences among threads and show program structures explicitly. The over-approximated CFGs represent all possible execution paths at run-time though they may contain some unreachable paths. Therefore, our CFGs are useful for a program analysis or diagnosis based on graph theory or control-/data- flows. Second, we present a new logical semantics of Esterel. Explicit synchronization control with imperative features is an important characteristic of Esterel. Esterel has some versions of logical semantics that provide simple and good formalisms for formal verification. However, the entire synchronization proces...
Choe, Kwang-Mooresearcher최광무researcher
한국과학기술원 : 전산학과,
Issue Date
418709/325007  / 020035083

학위논문(박사) - 한국과학기술원 : 전산학과, 2010.2, [ ix, 94 p. ]


static analysis; logical semantics; control flow graph; Esterel programming language; reactive system; 반응형 시스템; 정적 분석; 논리적 의미구조; 제어 흐름 그래프; Esterel 프로그래밍 언어

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