This dissertation presents a new technique to generate test sequence from a specification in System Description Language (SDL), in order to verify the conformity of the implementation with the specification.
In the generation of test sequences, concept of internal event and SIO(Set of Input Output) are introduced and an improved determinization algorithm is applied. From the state transition graph of the SDL specification, a global I/O FSM (Input/Output Finite State Machine) is obtained, it contains the external events having interactions with the SDL environment and the internal events being not visible from the SDL environment. A concept of the internal event allows to resolve the state space explosion. Afterwards, the global I/O FSM is transformed into a reference I/O FSM which is deterministic and minimal in accordance with the trace equivalence.
To resolve a possible problem of non-deterministic FSM into deterministic FSM, enhanced determination algorithm is applied. And UIO (Unique Input Output) sequences are used basically in the generation of test sequences. But for an identification sequence of the state without UIO sequence, the new concept of SIO is introduced to obtain a shorter length than the signature of the UIO method. Finally, to illustrate, the generation of optimized test sequences for the Inres protocol is presented.