(A) microprogrammed computer architecture for software reliability improvement

Abstract

Various aspects in the design and implementation of a software fault tolerant computing system are investigated. Specific subjects studied or results obtained include logical structure of the fault-tolerant program (FTP) processing system, algorithms to process FTP, design and implementation of a minicomputer system to process FTP, design of a software package for the simulation of FTP processing system, and algorithms to detect parallelism. Proposed logical structure of the FTP processing system has dual processor architecture and utilizes Validation and Recovery Storage (VRS) to save and restore the state vectors produced during execution of an FTP. Developed algorithms reduce both storage overhead and time overhead by overlapping main stream computation and validation procedure. The logical structure is physically designed and partially implemented. $M^3$ is a microprogram controlled multi-minicomputer system which has special architecture to process FTP. A duplex memory and a CAM memory subsystems are suggested for VRS. The distinctive characteristics of specifications of $M^3$-a are a multiprocessor architecture with FORK and JOIN control primitives, dynamic user microprogramming using main memory as WCS, a multi-word accessible memory structure, an FTP processable architecture, and a bit-slice microprocessor based CPU. A simulation package, FTPSIM is developed for FTP processing system. Four types of FTP processing system models can be simulated in the various system environments of FTP. FTPSIM interprets model descriptions to generate GPSS models. Finally, algorithms to detect parallelism of a structured parallel program are developed although these are not directly applicable to the FTP processing system at present. This phase of research is just an initiation stage looking forward to the software fault-tolerance for the parallel processing systems.