Remote memory access delay hiding techniques for distributed shared memory systems with ILP processors

Abstract

Computer systems with multiple processors are developed to solve the computation heavy applications effectively. Many commercial processors support multiprocessor systems in the symmetric multi processing(SMP) form. SMP is one of the shared memory multiprocessor systems which provide shared memory programming environment, and have a problem of limited scalability. To solve the scalability problem without changing programming environment too much, distributed shared memory(DSM) systems are invented. But, DSMs suffer its large remote memory access delays, and reducing the effect of the large delay have become a main design issue of DSMs. Modern processors use various mechanisms of instruction level parallelism(ILP) to extract maximum performance within the physically limited clock speed. The ILP mechanisms are based on speculations and out-of-order executions. So, using the ILP on a shared memory multiprocessor system may cause memory inconsistency and can pro-duce incorrect results. Without the ILP, the performance of the shared memory multiprocessor system will be too poor. And the ILP can also hide the large remote memory access delay of DSMs. Most processors which support both SMP and ILP have special instructions which control memory access ordering by stalling pipeline until desired conditions are met. With its large remote memory access delay, DSMs also have different memory access characteristics over SMP. SMP systems use the cache coherence uniform memory access(CC-UMA) scheme and have monolithic memory architecture, so all the memory areas are shared and identical to the all processors. But, DSMs use the cache coherence non uniform memory access(CC-NUMA)scheme and have two different memory types, one is a private memory which is located at the same node with each processor and other processor cannot access it directly, another is a shared memory which is shared by all the processors and may be located on another node. So, the shared memory access may ha...