Unexpected dual cracks in chip-ceramic substrate interconnect: Unveiling the mechanism behind simultaneous cracking at both the top and bottom of a solder joint

Abstract

Chip-ceramic interconnect is increasingly vital in high-density IC especially in high-frequency applications, making the reliability of solder joints with underfill material in this case a significant concern. In this study, unexpected simultaneous cracking at both the top and bottom of a solder joint was noted after 500 thermal cycles. Crack 1 propagated along Ti/Pt/Au/SAC305 interface on Si chip side while crack 2 propagated along the solder/IMC interface on AlN HTCC substrate side, which significantly contrasted with prior researches based on FR4 substrate where single cracking typically occurred at one interface. The emergence of two cracks was attributed to tensile stress induced by CTE disparities among different components, including the underfill, which caused two stress interfaces. The FEA results indicated higher stress and strain levels on FR4 substrate compared to AlN, thus facilitating easier crack initiation and more severe crack propagation. The nanoindentation results showed a difference in elastic modulus between the IMC and beta- Sn phases, leading to stress concentration during thermal cycling which initiated crack. The increased brittleness of IMC contributed to partial penetration of the crack into the IMC layer during propagation. A strategy to enhance the reliability of the solder joint was also proposed.