Design techniques for power efficient and fast response hybrid DC-DC converter ICs

Abstract

In recent studies, numerous hybrid DC-DC converters have demonstrated superior efficiency and power density when compared to traditional buck converters. However, to utilize these hybrid DC-DC converters effectively, a meticulous design approach is essential. Typically, hybrid converters excel in specific applications, dominating conventional power converter topologies. This paper presents two DC-DC converters specifically designed for high-voltage, high-power applications and compact mobile applications. Part 1 of this paper presents a 48V-to-1V quadruple step-down (QSD) DC-DC converter. The QSD comprising 4 parallel-inductors and 3 series-capacitors can efficiently supply up to 10A with fully monolithic 12V LDMOS by lowering the switching voltage to be quartered. The hysteretic copied on-time (HCOT) control allows clockless synchronization of 4-phase QSD without collapsing series-capacitor voltages. The 2-phase all-hysteretic (2× slew rate) mode is also presented for voltage droop mitigation under extreme load fluctuations. The chip fabricated in 0.18μm BCD shows a peak efficiency of 88.5% and achieves Δ80mV sag and 1μs 2%-recovery time for a 6.3A/50ns load transition. Part 2 of this paper presents a parallel switched capacitor (PSC) hybrid DC-DC converter design methodology that can find a structure suitable for any given target voltage conversion ratio (VCR$_{Target}$). The proposed chip, fabricated using a 28nm CMOS process, occupies a die area of 3.08mm$^2$. The chip is designed for 3.6V-to-1V voltage conversion ratio (VCR) and is capable of supplying up to a 1.5A load current. The PSC hybrid converter employs a 0.56μH (1608) inductor, a 10μF C$_1$ capacitor (1608), and die-attached 4.7μF C$_2$ and C$_3$ (1005). Excluding C$_2$ and C$_3$ vertically placed on the die, the total module area comes to 5.64mm$^2$. Despite such a compact footprint, the chip achieves a peak efficiency of 94.1% at a load current of 0.4A. These results highlight the effectiveness of our proposed PSC hybrid converter design methodology.