I/O layout-aware task scheduler입출력 레이아웃을 고려한 작업 스케줄러

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The Non-Uniform Memory Access (NUMA) architecture, containing multiple CPUs, causes non-uniformity in I/O operation. Within a NUMA node, communication between the CPU and I/O devices takes place over Direct Cache Access (DCA), whereas communication between the CPU and I/O devices across distant NUMA nodes takes place over Direct Memory Access (DMA). DMA results in an increased incidence of cache misses during identical network operations, thereby necessitating a greater consumption of CPU cycles. Therefore, utilizing the NIC within other NUMA nodes leads to inefficient usage of CPU resources. To use CPU cycles efficiently for I/O operation, systems require to take into account the non-uniformity in I/O. There are two existing approaches to designing systems that reflect the non-uniformity in I/O: i) The scheduler allocates tasks on the NUMA node where the requested NIC exists. ii) The system extends a NIC connection to the other NUMA nodes so all nodes utilize DCA. However, the first approach does not work for the dynamic workload since it statically allocates resources. The hardware methodology only accommodates a single NIC system, resulting in considerable synchronization overhead arising from simultaneous access by all nodes to a singular NIC.In this work, we design a I/O layout-aware scheduler that handles dynamic workload while preserving the scalability inherent in general-purpose schedulers. Tasks are categorized into local or remote tasks based on where they are requested. Each node preferentially processes local tasks and processes remote tasks if there are no local tasks. To overcome the limitation of static allocation scheduling, we adopt work stealing to achieve work conservation under dynamic workload. Lastly, different NUMA affinitive tasks are mixed in the node when the processor takes remote tasks. To solve this problem, we mark the worker that processes remote tasks. Our scheduling algorithm demonstrates a throughput improvement of up to 48\% in the case of a balanced workload compared to the existing general-purpose scheduler. Our scheduler shows up to 78\% higher throughput for an unbalanced workload than strict boundary scheduling.
Advisors
문수복researcher
Description
한국과학기술원 :전산학부,
Publisher
한국과학기술원
Issue Date
2024
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전산학부, 2024.2,[iv, 27 p. :]

Keywords

NUMA architecture▼aDirect memory access▼aDirect cache access▼aCPU▼aI/O▼aNIC▼aGeneral-purpose scheduler▼aWork stealing scheduler; NUMA 구조▼a직접 메모리 접근▼a직접 캐시 접근▼aCPU▼a입출력▼a네트워크▼a범용 스케줄러▼a작업 도용 스케줄러

URI
http://hdl.handle.net/10203/321790
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=1097315&flag=dissertation
Appears in Collection
CS-Theses_Master(석사논문)
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