Power gating switch cells (PGC) are inserted to cut the supply current from the power sources to the circuits that are not in use. PGCs are allocated larger sizes to prevent IR-drop violations during floorplanning. After placement, PGCs are resized to reduce the unnecessarily large size, which acts as a routing blockage. The challenge is the significant runtime required to verify IRdrop constraints whenever PGC sizes are changed. Our approach consists of two components: (1) fast IR-drop prediction using ML models and (2) routability-driven heuristic algorithm to optimize PGC sizes. Experimental results demonstrate that the predicted IR-drop closely aligns with the reference, with a mean absolute percentage error (MAPE) of $2.9%$. The proposed algorithm successfully removes all routing design rule check violations (DRV), including those that could not be addressed by previous methods.