Ultra-low jitter low-power W/D-band phase-locked loop using power-gating injection-locked frequency multiplierbased phase detector파워게이팅 인젝션 락킹 주파수 체배기 기반의 위상 감지기를 이용한 초저잡음 저전력 W/D-밴드 위상고정루프
Proposed are an ultra-low jitter low-power phase-locked loop using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) and an operating method thereof. The proposed PG-ILFM PD includes a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal SREF and a fundamental sampling phase detector (FSPD) configured to receive an output signal SILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO).