A D-band wideband low-noise amplifier (LNA) is presented, which consists of five-cascaded differential amplifiers fabricated in a 40-nm RF CMOS process. Each stage has a common gate (CG) configuration to have low noise at the high frequencies. Triple-coupled transformers are introduced in all stages to increase gains and to make interstage matchings, which have asymmetrical frequency responses. The input and output Q factors of the transformers are tailored to achieve staggered matchings for wideband characteristics. This allows it to have a flat gain of 19.5-20.5 dB and a noise figure of 6.2-9.0 dB at 136-159 GHz. It shows a peak gain of 20.9 dB at 153 GHz and a noise figure of 6.2 dB at 148 GHz. It has a minimum IP1dB is -19.7 dBm, and occupies 0.24 mm(2) including I/O pads with the core size of 0.09 mm(2). It consumes a total dc power of 49 mW from a 1-V supply.