A 187dB FoMS 46fJ/Conv. 2nd-order Highpass ΔΣ Capacitance-to-Digital Converter
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Jung, Yoontae | ko |
| dc.contributor.author | Oh, Sein | ko |
| dc.contributor.author | Koo, Jimin | ko |
| dc.contributor.author | Park, Seunga | ko |
| dc.contributor.author | Suh, Ji-Hoon | ko |
| dc.contributor.author | Cho, Donghee | ko |
| dc.contributor.author | Ha, Sohmyung | ko |
| dc.contributor.author | Je, Minkyu | ko |
| dc.date.accessioned | 2023-12-04T07:01:57Z | - |
| dc.date.available | 2023-12-04T07:01:57Z | - |
| dc.date.created | 2023-11-29 | - |
| dc.date.issued | 2023-06-11 | - |
| dc.identifier.citation | 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) | - |
| dc.identifier.uri | http://hdl.handle.net/10203/315686 | - |
| dc.description.abstract | The proposed capacitance-to-digital converter (CDC) achieves 187dB FoMS, which is >2x improvement over the state-of-the-art, with FoMW of 46fJ/Conv.-Step. We employ a highpass ΔΣM in CDC applications for the first time while using loop filters based on power-efficient floating inverter amplifiers (FIAs). | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | A 187dB FoMS 46fJ/Conv. 2nd-order Highpass ΔΣ Capacitance-to-Digital Converter | - |
| dc.type | Conference | - |
| dc.identifier.scopusid | 2-s2.0-85167620032 | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) | - |
| dc.identifier.conferencecountry | JA | - |
| dc.identifier.conferencelocation | Kyoto | - |
| dc.identifier.doi | 10.23919/vlsitechnologyandcir57934.2023.10185219 | - |
| dc.contributor.localauthor | Je, Minkyu | - |
| dc.contributor.nonIdAuthor | Koo, Jimin | - |
| dc.contributor.nonIdAuthor | Park, Seunga | - |
| dc.contributor.nonIdAuthor | Suh, Ji-Hoon | - |
| dc.contributor.nonIdAuthor | Cho, Donghee | - |
| dc.contributor.nonIdAuthor | Ha, Sohmyung | - |
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