Adaptive error management system for low latency NAND flash memory under process variation

Abstract

NAND flash memory is becoming smaller and denser to have a larger storage capacity as technologies related to fine processes are developed. As a side effect of high-density integration, the memory can be vulnerable to circuit-level noise such as random telegraph noise, decreasing the reliability of the memory. Therefore, low-density parity-check code that provides multiple decoding modes is adopted in the NAND flash memory systems to improve error tolerance of flash memory. The error correcting capability of soft-decision decoding is powerful but it increases read latency because it requires multiple sensing and iterative decoding. In this thesis, we propose two error management schemes to reduce the read latency of NAND flash memory. First, we propose a dynamic error recovery flow (ERF) scheme using machine learning (ML). Unlike conventional static ERF which applies decoding modes sequentially, dynamic ERF predicts an optimal decoding mode guaranteeing successful decoding and minimum read latency and applies it directly to reduce read latency. Due to process variation incurred in memory manufacturing, memory characteristics are different by chips and it becomes difficult to apply a trained prediction model to different chips. Therefore, we consider ERF prediction based on meta learning to deal with varying input and output relationships by chips due to process variation. Meta learning method reuse knowledge learned from source tasks to fastly adapt the model to perform its task without any loss of performance in different chips. Next, we consider an adaptive quantization scheme for triple-level cell flash memory that adjusts soft sensing reference voltages depending on the memory channel state. Adaptive quantization of soft sensing can maximize the mutual information between the programmed state and log-likelihood ratio information for decoding. The error correcting performance can be enhanced considerably so that decoding time decreases. Numerical results validate the advantages of the proposed methods with high prediction accuracy in multiple chips.