Reliability assessment on electronic interconnects by S-parameter pattern analysis

Abstract

Despite the continuous demand for higher computing power, plateauing is performance of almost every building block including transistors, memories, and processors. With the aggressive down-scaling of advanced integrated circuits (ICs), the electrical interconnects have become the bottleneck of both reliability and performance of whole electronic systems. In order to resolve the reliability issues, Institute of Electrical and Electronics Engineers (IEEE) laid down a roadmap thrusting the digital twin: a combination of reliability physics and artificial intelligence. Previous research works have proposed numerous reliability assessment tools using DC resistance, S-parameter, RF impedance, Time Domain Reflectometry, etc. Commonly, the methods suffer from noise and irregularities over a wide range of frequency. They also have difficulties in distinguishing healthy interconnects under external stresses from faults and in deciding root causes of the defects. A research goal of this dissertation is to develop reliability assessment and health management methods on electrical interconnects using S-parameter pattern analysis, covering collective aspects of the digital twin. In order to do so, this dissertation takes 3 research strategies: first, to analyze performance variation of healthy interconnects using S-parameter patterns

second, to track the evolution of the interconnect failures by observing the S-parameter patterns

third, to determine root cause and severity of defects by deep learning of the S-parameter patterns. It is expected that the proposed reliability assessment method overcomes the limitations of existing methods, performing every job required by the digital twin roadmap with a single tool: the S-parameter pattern analysis.